Ferroelectric memory and other types of semiconductor memory are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memory commonly includes groups of memory cells, wherein the respective memory cells comprise single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) arrangements, in which data is read from or written to the memory using address signals and/or various other control signals. Ferroelectric memory cells include at least one transistor and at least one capacitor because the ferroelectric capacitors serve to store a binary bit of data (e.g., a 0 or 1), and the transistors facilitate accessing that data.
Ferroelectric memory is said to be non-volatile because data is not lost when power is disconnected there-from. Ferroelectric memory is non-volatile because the capacitors within the cells are constructed utilizing a ferroelectric material for a dielectric layer of the capacitors. The ferroelectric material may be polarized in one of two directions or states to store a binary value. This is at times referred to as the ferroelectric effect, wherein the retention of a stable polarization state is due to the alignment of internal dipoles within Perovskite crystals that make up the dielectric material. This alignment may be selectively achieved by applying an electric field to the ferroelectric capacitor in excess of a coercive field of the material. Conversely, reversal of the applied electric field reverses the internal dipoles. The polarization of a ferroelectric capacitor to an applied voltage may be plotted as a hysteresis curve.
As in most modern electronics, there is an ongoing effort in ferroelectric memories to shrink the size of component parts and/or to otherwise conserve space so that more elements can be packed onto the same or a smaller area, while concurrently allowing increasingly complex functions to be performed. Accordingly, memory layout architectures have been developed to conserve the amount of area on a semiconductor wafer or die needed to implement relatively large scale memories, such as 64 megabit devices. Such memory architectures are typically divided into blocks, sections, segments, rows and/or columns. For example, a 64 megabit memory may include eight 8 megabit blocks, where each block may comprise eight 1 megabit sections, with each section having 32 segments and each segment comprising an array of 512 rows or memory cells and 64 columns of memory cells. Bitlines, wordlines, platelines and sense amplifiers are utilized to read data from and to write data to the memory cells. Generally, bitlines and sense amplifiers are associated with cell columns, while wordlines and platelines are associated with cell rows.
Additionally, some type of configuration data is generally associated with circuit arrangements that include ferroelectric memory and/or application specific integrated circuits (ASIC's) employing on-chip ferroelectric memories. Such configuration data may include, for example, redundancy programming information, die identification data, serial number data, circuit trim data, reference voltage trim data, etc. The configuration data is typically accessed at every startup and utilized at that or a later time to configure a device for operation and/or to execute initialization and/or diagnostic activities. Given the ongoing desire to increase packing densities, it would be desirable to be able to store and handle, in an area efficient manner, ever increasing amounts of configuration data needed to support increasingly complex applications.